Interrupts are subjected to priority. The interrupt priority scheme is hardware-determined, but in the interest of portability it is abstracted by the Windows HAL. During interrupt processing, interrupts from lower-priority interrupts are masked so that they remain pending until the current interrupt processing completes. Following interrupt processing during which interrupts themselves are disabled, the operation system returns to its essor is once normal operating mode with the processor reset once more to receive interrupt signals. The proc again enabled for interrupts.
Strictly speaking, on an , there is a class of interrupts used for switching between the user level and privileged OS code. Although this involves interrupt processing on the Intel
In Windows, hardware device interrupts are serviced by an interrupt service routine, or ISR, which is a standard device driver function. Device drivers are extensions of the OS tailored to respond to the specific characteristics of the devices they understand and control. The ISR code executes at the interrupt level priority , with interrupts at the same or lower level disabled. An ISR is high priority by definition since it interrupts the regularly scheduled thread and executes until it voluntarily relinquishes the processor (or itself interrupted by a higher-priority interrupt).
The ISR normally signals the device to acknowledge the event, stops the interrupt from occurring, and saves the device status for later processing. It then schedules a deferred procedure call (DPC) to a designated routine that performs the bulk of the device-specified work associated with interrupt processing. DPCs are a special feature of Windows designed to allow the machine to operate enabled for interrupts as much as possible. DPC code executes at a higher priority than other OS privileged modes, but one that does not disable further interrupts from occurring and being serviced.
The DPC mechanism in Windows keeps the machine running in a state enabled for interrupts as much as possible. This architecture is especially useful with Intel PC Hardware where many devices connected to a single PCI bus can share the same Interrupt Request Queue (IRQ) level. DPC routines execute from a separate DPC dispatcher queue, which Windows empties before it calls the Scheduler to re-dispatch an ordinary kernel or application thread. A typical function carried out by a DPC routine is to reset the device for the next operation and launch the next request if one is queued. When the DPC completes, a high-priority kernel or device driver thread then marks the I/O function complete. At the end of this chain events, a waiting thread transitions to the ready state, poised to continue processing now that the I/O it requested has completed.
When an interrupt occurs, the thread executing loses control of the processor immediately. When the DPC performing the bulk of the interrupt processing completes, the Windows Scheduler checks the Ready Queue again and dispatches the highest-priority thread. The interrupted thread does not necessarily regain control following interrupt processing because a higher-priority task may be ready to run. This is variously known as preemptive scheduling, preemptive multithreading or preemptive multitasking.